Integrated circuits are well known devices which provide complicated circuit structures on a single substrate or "chip". Since their inception, these devices have grown more complicated with increasingly large numbers of devices required for new applications. At the same time, the cost of these devices has dropped dramatically. One example of the trend in the integrated circuit industry is computer memory devices. Early memory devices contained the equivalent of one thousand memory cells on a single chip. Today, computer memory devices may contain a million or more memory cells. The corresponding cost per memory cell has dropped by at least an order of magnitude.
This trend exists in all phases of the integrated circuit industry. The ability to incorporate large numbers of devices on a single chip has fostered new classes of devices which were not possible with prior technology. Microprocessors and digital signal processors have appeared relatively recently and the complexity of these devices have pushed known process technologies to its limits. Early microprocessors were implemented as four and eight bit devices while current microprocessors have been developed with sixteen and thirty two bit data paths. This has resulted in a four-fold increase in circuit density.
One technique designers have used to fabricate more complex devices is to increase the size of the integrated circuit substrate. Another well known technique is to shrink the size of the individual components of the device. Each of these techniques has problems. For example, as the size of the integrated circuit substrate increases, processing yield decreases. This is because the silicon wafers used to manufacture the chips often have crystalline defects which may render components non-functional. Therefore, the size of a semiconductor chip may be limited by the defect density of the silicon wafer used to manufacture the chips.
Most known integrated circuit manufacturing processes rely in part on photolithographic processes which have a finite ability to produce small objects. In other words, the resolution of the photolithographic process limits the amount of reduction possible in producing small components. Furthermore, since the wavelength of light is relatively long with respect to semiconductor devices in the range of 1 micron, the wavelength of the light used in the photolithographic process also limits the size reduction possible with the process.
Another limiting factor with photolithographic processing is the alignment of the masks used to form the various layers of the device. A minute misalignment in these masks will produce unsatisfactory results. As device sizes grow even smaller, the alignment of the various masks grows more critical.
The processing environment for small semiconductor devices also becomes more critical as device size grows smaller. For example, a particle of material as small as 1 micron in the processing environment may render a small semiconductor device non-functional.
Another problem facing designers today is the fact that as devices grow more complicated, design cycles grow longer. This results in increased cost for producing a new design. However, competitive pressures demand that new designs be produced for lower cost per device than prior designs. As known techniques for increasing the density of integrated circuits have approached theoretical limits, designers have sought new methods for increasing the density and complexity of integrated circuits while providing a cost savings over prior designs
In response to these demands, designers have turned to multilayer interconnection structures to provide greater flexibility in arranging the devices on the semiconductor substrate. One known multilayer interconnection technique is to deposit a first layer of interconnecting metallization on the integrated circuit. An insulating layer is then deposited over the first metallization layer. In some cases, the integrated circuit is planarized somewhat by addition of a layer of photoresist material and etching the photoresist and an insulating dielectric layer to planarize the device as much as possible. A series of holes are then etched through the insulating dielectric layer in the locations where interconnections are desired. Finally, a second layer of metallization is deposited over the first layer of metallization and insulating layer thus contacting the first metallization layer in the areas where the holes are etched in the insulating dielectric layer. The interconnections between the two metallization layers are referred to as "vias".
While this technique does provide increased flexibility in arranging components on the integrated circuit substrate, small detents or depressions are formed at the via locations and the top surface of the resulting device is not planar especially if the first layer of metal is on more than one level as will be discussed below. Since this surface is not planar it is not possible or at least very difficult to deposit any further interconnecting or device layers on the device. No technique is known which allows the deposition of one or more interconnecting layers while rendering the resulting device completely planar. A planar device is highly desirable because such a device would permit the creation of additional interconnecting or device layers and allow a virtually unlimited potential ability to vertically stack components on an integrated circuit substrate.
Furthermore, during photolithographic processing, in a non-planar device, it is difficult if not impossible to focus on all areas of the integrated circuit. In other words, some portions of the integrated circuit will be in focus while others will not. As additional layers are added, the effects of non-planarity are additive, thus compounding the above mentioned problems.
In devices where multilayer metallization is desired, non-planar devices pose another significant problem. This is especially true in MOS devices which employ field or insulating oxides between the individual devices. In this case, metal deposited over oxide areas will be at a different level than the metal over the device diffusions. The dielectric layer disposed over the metal and device layers will similarly have a surface at several different levels. Because of this level offset, vias etched on these different levels will have different widths. Specifically, the vias on the higher level will be etched wider than the vias on lower levels. The vias on the second level will have a higher aspect ratio than the vias on the first level creating problems when the second layer of metallization is deposited. Specifically, the via holes on the lower level may not be etched sufficiently to allow contact with the underlying metal or the via holes may not completely fill with metal when the metal is deposited on the integrated circuit. In other cases it may be necessary to overfill some via holes to insure all via holes are filled, thus compounding the non-planarity problem.